1. Field of the Invention
The present invention relates to a device under test (DUT) tester using a redriver, capable of more effectively testing the DUT, which is a predetermined semiconductor device, by applying an electrical signal to the DUT and measuring the electrical signal. In more particular, the present invention relates to a device under test (DUT) tester by using a redriver, which includes a DUT test unit, a printed circuit board (PCB) provided therein with connectors for the connection with the DUT test unit, one DUT or more horizontally arranged on the PCB, and redrivers horizontally provided under the PCB and one-to-one matched with one or more DUT to compensate for the distortion of the signal integrity of test signals caused according to the variation of the transmission distance.
2. Description of the Related Art
In order to properly ensure the functionality and the reliability of semiconductor devices, the manufacturers of the semiconductor devices test the semiconductor devices before delivering the semiconductor devices to venders or customers.
In general, the failure probability of a device under test (DUT) is most highly represented during a predetermined time in the initial stage, and, thereafter, almost uniformly represented until the life span of the DUT is terminated.
The DUT is tested under an environment severer than a general use environment (e.g., room temperature) of the DUT, such that the failure of the DUT that may be found under the general use environment of the DUT can be more rapidly detected. Accordingly, the potential failure of the DUT, which may be found after DUTs have been come onto the market, can be detected.
Hereinafter, a DUT tester according to the related art will be described with reference to FIGS. 1 to 4.
FIG. 1 is a view showing the structure of the DUT tester according to the related art having a printed circuit board (PCB) equipped with test sockets vertically arranged thereon. In an initial DUT tester, a circular PCB is prepared to test DUTs one by one. Thereafter, for the purpose of test convenience, a plurality of DUTs are vertically stacked on each other and tested in a test chamber.
As shown in FIG. 1, the initial DUT tester has a wall vertically installed therein. A test unit (mainly a unit such as a PC provided therein with a microprocessor or a controller) is installed in one space of a wall. An opposite space of the wall is used as a chamber, and provided therein with test sockets in such a manner that the DUTs are installed in the test sockets. In addition, since the DUT test unit is linked with each DUT through a cable, as the number of DUTs to be tested is increased, the number of cables must be increased corresponding to the number of the DUTs.
Accordingly, the DUT tester shown in FIG. 1 has a limitation in increasing the number of DUTs since the DUTs are installed on a vertical surface. In addition, there is a limitation in automating the installation or the uninstallation of the DUTs.
Therefore, in order to solve the problem related to the DUT tester of FIG. 1, increase the number of DUTs to be tested, and facilitate the installation of the DUTs on the PCB or the uninstallation of the DUTs from the PCB, Korean Patent Registration No. 10-0916209 (issued on Sep. 1, 2009) discloses a test system for a DUT in which DUTs are horizontally installed.
In a DUT tester of FIG. 2, since a PCB having a DUT installed therein may be easily introduced or withdrawn in a horizontal direction, the DUT may be easily installed or uninstalled.
In addition, since cables connecting a vertically installed DUT test unit with DUTs are installed in the PCB (not shown), the cables may not be exposed to the outside.
Further, in the DUT tester of FIG. 2, DUTs are installed on the PCB, and controllers or test units matched with the DUTs are installed under the PCB. Since each controller is electrically connected to the DUT, a connection characteristic is improved, and a test processing rate is increased corresponding to 1.5 Gbps which is the transfer rate of an interface.
However, the DUT can be tested in FIG. 1 even if only one controller is installed outside the chamber, but controllers must be installed by the number of the DUTs in FIG. 2.
In particular, since the controller or the test unit used in the DUT tester is expensive and represents weak heat resistance, the failure probability of the controller may be increased when testing the DUT.
As shown in FIG. 3, in order to solve the problem related to the DUT tester of FIG. 2, controllers or test units one-to-one matched with each DUT are provided outside the chamber, and each test unit is linked with each DUT through the inner cable of the PCB.
Accordingly, even if only one controller or test unit, which is expensive and represents weak heat resistance, is provided, the DUT can be tested.
However, even if the inner cable of the PCB is used in FIGS. 2 and 3, the number of inner cables is required by the number of DUTs. In addition, fine cables may cause severe degradation to the signal integrity of test signals due to the high-temperature heat in the test chamber.
Particularly, although the DUT tester shown in FIGS. 2 and 3 according to the related art can easily test DUTs at a conventional transfer rate of 1.5 Gbps of an interface for transferring test signals, as the interface transfer rate is increased to two times or four times the transfer rate, that is, 3 Gbps or 6 Gbps, the signal integrity of the test signal is degraded according to the variation of the transmission distance while the test signal passes through the PCB. Accordingly, even if the interface represents the high transfer rate, it is impossible to exactly test DUTs at a test speed suitable for the interface.
In other words, the DUT tester according to the related art significantly degrades the signal integrity of a test signal according to the variation of the transmission distance regardless of whether controllers are one-to-one matched with DUTs as shown in FIG. 2, or whether the controllers or test units are provided outside the chamber as shown in FIG. 3.
FIG. 4 is a view showing the degradation of the signal integrity in the case that DUTs are horizontally arranged on a test printed circuit board according to the related art.
Since a DUT 1 of FIG. 4 is located close to the interface or a test unit, the transmission distance of the test signal is short. Accordingly, the test signal is transferred to the interface or the test unit without the signal distortion.
However, since the distance between a DUT 2 of FIG. 4 and the interface or the test unit is longer than the distance between the DUT 1 of FIG. 4 and the interface or the test unit, the transmission distance of the test signal is increased. Therefore, test signals are transferred to the interface or the test unit in the state that the test signals are significantly distorted. Since the degradation of the signal integrity according to the transmission distance is more increased as the transfer rate is increased, the desirable signal integrity may not be obtained corresponding to the transfer rate.